The present invention relates in general to programmable logic devices (PLDs), and in particular to a novel PLD product that realizes high logic density by combining several smaller PLDs on a multi-chip module substrate.
System Designers are increasingly challenged with the dichotomy of increasing functionality and decreasing form-factor. There are strong motivating factors behind this requirement, but few resources to assist engineers to meet the demands. One of the key resources is integration of electronic circuitry into fewer separate components.
At lower logic densities this is often done by integrating multiple small and medium scale logic functions into PLD-type devices. This integration reduces device count, and the enhanced flexibility of programmable logic allows increased system functionality that was previously unavailable in standard logic functions. In systems with more than a few thousand gates, high-density PLDs provide significant part-count reductions. This frequently occurs during a second-phase of a product, during a product shrink or repackaging.
For designs that go into high volume productions (thousands of units) it is often cost effective to develop a semi-or full-custom logic device such as a gate array or application specific integrated circuit (ASIC) to achieve the highest integration and maximum cost reduction. The tradeoff of using custom devices is that once they are manufactured, any modifications incur a second design charge. Corrections for logic errors in the design double the development cost, making it critical that the design is correct and complete prior to manufacturing the custom device.
Designers desire the cost and integration benefits from the custom-solutions, but must manage the risk and cost of design errors. Several strategies have evolved to address this problem, with the two most common being design simulation, where a software model of the design is tested with simulated test vectors in an attempt to find error conditions, and emulation or prototyping, where a hardware model of the design is tested with the same vectors, to attempt to find any design errors. The principle difference between the two validation methods is how quickly they can identify errors in a design.
Simulation is the easiest way to verify a custom-logic design since it can be done in a virtual sense, using a software model of the design. There are, however, pitfalls associated with simulation. The first is that simulation is very slow. A software model of a logic design is inherently slower than the corresponding hardware. Although recent advances in parallel computing hold the promise to enable faster simulation, the speed with which test vectors can be sent into the software model sets an upper limit to the exhaustiveness of testing that is achievable in a fixed time.
Simulation is also limited by the ability of an engineer to generate test vectors and the corresponding responses that xe2x80x9cshouldxe2x80x9d be returned to the device. This approach requires that the engineer generate accurate vectors, and is limited by the human-bandwidth available to assemble the test suite. Formal verification, where mathematical proofs are used to test models rather then relying on exhaustive test vectors, will alleviate the burden on the designer, but the inherent slowness of simulation puts an upper limit on its usefulness.
Emulation of a logic design uses a hardware model instead of a software model to validate the test and expect vectors for a design. While emulation still requires the generation of a test suite, the hardware-based emulation model allows a much faster cycle, since the vectors may be applied much faster to the hardware system than to the software model. With emulation hardware being combined with the formal proof validation techniques mentioned earlier, hardware emulation emerges as the ideal method to validate custom designs.
Hardware prototyping systems rely on a set of reconfigurable PLDs in a generic interconnect structure. The design is mapped into the uncommitted logic resources of the PLDs in the system. Two such prototyping products have been developed by Altera Corporation of San Jose, Calif., and are fully described in separate U.S. patent applications with Ser. Nos., 08/206,774, and 08/348,280.
Emulation or prototyping systems, however, tend to be more costly and, while they provide higher density, may not do so very efficiently. Due to the architecture of most PLDs, the efficiency of the design mapping is around 50-70%, depending on the type of PLD. Often the PLDs are used for routing as well as logic, which further reduces their effective density. Thus, to achieve a useful density of 100,000 gates, it may be necessary to provide 250,000 available gates. This would require twenty-five 10,000 gate devices which would typically be mounted on a printed circuit board with support hardware and cooling equipment. The application of such hardware prototyping systems is therefore limited to those designs that can justify the costs associated with such prototyping systems.
There is therefore always a need for more cost-effective programmable logic products that provide higher densities of usable logic.
The present invention provides, in a single cost-effective, high performance package, an apparatus for multiplying the gate count of the highest density programmable logic device available in monolithic silicon.
Broadly, the present invention provides a programmable logic apparatus in a single package which includes: a multilayer substrate having a top side and a bottom side, with the bottom side having a plurality of external connectors; a plurality of prepackaged monolithic PLDs mounted on the top side of the multilayer substrate; and a field programmable interconnect (FPIC) die attached on the bottom side of the multilayer substrate, wherein the FPIC die on the bottom side of the multilayer substrate is protected by a ceramic lid. The multilayer substrate further includes conductive nets and vias through which the plurality of PLDs are electrically coupled to the FPIC and the external connectors. Therefore, by providing programmable interconnection between a plurality of PLD packages, the apparatus of the present invention offers a single programmable logic package with logic capabilities several factors higher than that available by the highest monolithic PLDs. Also, the two-level packaging process of the present invention eliminates several manufacturing problems associated with conventional multichip module designs.